VSORA, a provider of high-performance silicon IP solutions for AI, digital communications and ADAS applications, has unveiled a family of PetaFLOPS computational companion chips to accelerate L3 through L5 autonomous vehicle designs.

Tyr, the first full silicon solution from VSORA, uses a proprietary, scalable architecture to achieve enhanced performance built on the VSORA AD1028 platform. Delivering between 258-trillion and 1,032-trillion operations per second, at a consumption rate as low as 10 watts, Tyr allows users to implement autonomous driving functions that were not previously commercially viable.

Encompassing a family of chips (Tyr1, Tyr2 and Tyr3), Tyr will also provide a fully programmable architecture that tightly couples digital signal processing cores with machine learning accelerators necessary to design autonomous vehicles ranging from L3 through to L5. The Tyr companion chip is both algorithm and host processor agnostic – and can be integrated into new or existing environments without the need to redesign full systems.

The modular architecture of the Tyr family is equipped to help customers overcome the challenges of autonomous driving. With a computational power of 1,032 TFLOPS, Tyr3 is capable of processing an eight-million cell particle filter using 16-million particles in less than 5 milliseconds.

The Tyr family is implemented using VSORA’s proprietary low-power architecture to achieve more than 80% usage efficiency approximating the theoretical maximum processing power. This eliminates the need for expensive multi-chip or hardware accelerator solutions, or special cooling systems.

The VSORA Tyr1, Tyr2 and Tyr3 will sample in Q4 2022, and be made available for in-vehicle use in 2024.